1. Field of the Invention
This invention relates to a method of interfacing with data and a data interface apparatus, and more particularly, to a data interface method and apparatus which interfaces data so as to eliminate EMI caused during data transmission. Also, the present invention is directed to a method and apparatus for driving a liquid crystal panel so as to vary a data transmission speed such that EMI is eliminated. In addition, the present invention is directed to a monitor driving method and apparatus for driving a monitor such that EMI is eliminated by varying a data transmission speed.
2. Description of the Related Art
Data interface requirements of various display devices have been increasing because of the frequent transmission of text information, video information, and other information. Also, data interface requirements have greatly increased because the amount and type of data, such as audio information, is now regularly transmitted with such text, video and other information to the display devices. The text information and the video information must be transmitted at a high speed such that the text and video information is used at an appropriate time. Accordingly, the text information and the video information occupy a high frequency band.
As will be explained in more detail below, the inventors of the present application discovered that, as the frequency band of such video and text information increases, an electromagnetic interference, hereinafter referred to as xe2x80x9cEMIxe2x80x9d, occurs in a data transmission line such as a data bus. Also, the EMI is also greatly increased at a display device such as a liquid crystal display (xe2x80x9cLCDxe2x80x9d) and a monitor apparatus especially when such video, audio and text information are transmitted to and displayed thereon.
Problems with EMI were recognized in conventional devices to exist only at a source driver and EMI was thought to be caused only by the large distance between the ASIC drive IC to the contact pads of the data driver. A conventional solution was to reduce EMI at the source driver by inserting noise filters, such as an EMI reduction filter or LC filter, at an ASIC data drive IC. Thus, it was attempted to smooth every output signal from the ASIC drive IC by putting the EMI filter, a shield or a grounding gasket between a data output pin and the drive IC pad. This solution proved to be very expensive and the EMI filter or reduction device causes a delay in signal transmission from the data output pin and also adds an additional complicated manufacturing process.
Another related solution is shown in FIGS. 1 and 2 in which a two port or multi-port system is used such that frequency of data transmission is reduced to reduce EMI.
Thus, instead of using an EMI filter or shield, a controller changes the period of data transmission. Such a multiple data transmission scheme has been used for a data interface apparatus for use in a display device such as an LCD or monitor in order to reduce EMI.
However, in such a device, EMI is still a problem because data transmission occurs at the same location along the clock signal where the clock frequency is constant. That is, data transmission occurs at either at the rising edge or the falling edge of the constant clock signal. Also, the multiple data transmission scheme complicates the data transmission line and severely limits the design freedom and capabilities of the data interface apparatus and the display apparatus and monitor.
More specifically, an LCD uses a liquid crystal panel driving apparatus having a dual bus structure as shown in FIG. 1 so as to reduce an EMI. In FIG. 1, the liquid crystal panel driving apparatus includes source driving integrated circuits(ICs) 12 for driving signal lines in a liquid crystal panel 10, a gate driving IC 14 for driving gate lines in the liquid crystal panel 10, and a timing controller 16 for controlling timing of the source driving ICs 12 and the gate driving IC 14. The timing controller 16 responds to a data clock DCLK received from a clock line CKL as shown in FIG. 2 and vertical and horizontal synchronizing signals VSYN and HSYN from a synchronizing signal line SSL to control operation timing of the source driving ICs 12 and the gate driving IC 14. The source driving ICs 12 are supplied with a source control signal via a source control line SCL while the gate driving IC 14 is supplied with a gate control signal via a gate control line GCL. The source control signal includes a transmission clock TCLK, as shown in FIG. 2, for indicating a transmission period of the video data. The timing controller 16 transfers video data from an external bus EB to the source driving ICs 12.
In order to reduce an EMI generated when the video data is transferred to the source driving ICs 12, the timing controller 16 is connected to the source driving ICs 12 via first and second internal buses FIB and SIB. The first internal bus FIB transfers red(R), green(G) and blue(B) data FIRD, FIGD and FIBD, as shown in FIG. 2, for odd-numbered pixels to the source driving ICs 12, whereas the second internal bus SIB transfers R, G and B data SIRD, SIGD and SIBD, as shown in FIG. 2, for even-numbered pixels to the source driving ICs 12. Accordingly, the timing controller 16 divides video data ERD, EGD and EBD received from the external bus EB into odd-numbered pixel data FIRD, FIGD and FIBD and even-numbered pixel data SIRD, SIGD and SIBD. The video data includes R, G and B data, each of which comprises a 6 bit signal. Accordingly, the external bus EB includes 18 bit lines, and each of the first and second internal buses FIB and SIB includes 18 bit lines, too. The odd-numbered pixel data and the even-numbered pixel data is simultaneously supplied to the source driving ICs 12, whereby data at the first and second internal buses FIB and SIB has a frequency equal to one half of the data at the external bus EB.
In addition, a transmission clock at the source control line SCL also has a lower frequency, which is reduced by xc2xd, compared to a data clock at the clock line CKL. For example, when the liquid crystal panel is an XGA-class panel, a frequency of the data at the external bus EB and a frequency of the data clock at the clock line CKL are 18 MHz and 65 MHz, respectively. A frequency of the data at the internal buses FIB and SIB and a frequency of the transmission clock at the source control line SCL are 9 MHz and 32.5 MHz, respectively, in the EMI measuring pattern. Accordingly, an EMI is reduced at a transmission line between the timing controller 16 and the source driving ICs 12.
In the liquid crystal panel driving apparatus as shown in FIG. 1, however, since a frequency of the data at the first and second internal buses FIB and SIB and a frequency of the transmission clock TCLK at the source control line SCL is locked, an EMI is not only significantly emitted at a frequency of the data and a harmonic frequency thereof, but also at a frequency of the clock and a harmonic frequency thereof. As a result, the liquid crystal panel driving apparatus of FIG. 1 fails to reduce an EMI below a desired, acceptable minimum level and within a range that has a negligible affect on the displayed image produced on the LCD or monitor.
In addition, U.S. Pat. No. 5,659,339 describes a device in which EMI is attempted to be reduced by phase-modulating a clock so as to spread out the EMI along the clock. However, this method only slightly reduces an amplitude of EMI and is not effective for significantly reducing or substantially eliminated EMI.
To overcome the problems described above, preferred embodiments of the present invention provide a data interface apparatus, a liquid crystal display apparatus, a monitor and method for transmitting data to a liquid crystal display or monitor, each of which is adapted to minimize and eliminate an EMI without complicating the structure or assembly process thereof.
According to at least one of the preferred embodiments of the present invention, a data interface apparatus is arranged to transfer data in such a manner that a speed of a clock used for data transmission is changed such that EMI is greatly reduced or substantially eliminated. It should be noted that the manner in which the clock speed used for data transmission is varied to eliminate EMI may include a plurality of variation schemes, including a pre-defined pattern of clock speed variation which is dependent upon, for example, a triangular wave or sinusoidal wave, a symmetric or asymmetric pattern, or a pattern which gradually changes the clock speed used for data transmission such that a data transmission speed is faster and then slower, or slower and then faster.
In addition, the specific mechanism used for varying the clock speed used for data transmission preferably includes a clock modulator in the form of an IC chip such as an ASIC chip, an electronic circuit or other electronic devices arranged to vary the clock speed used for data transmission to reduce EMI as described herein with respect to preferred embodiments of the present invention.
A data interface apparatus according to another preferred embodiment of the present invention includes a data input arranged to input data synchronized with a desired frequency of a data clock, a clock modulator arranged to modulate the data clock to provide a modulated clock having a frequency which is varied within a certain range of frequency band located around a desired target frequency, and a data timing controller responsive to the data clock and the modulated clock to vary a data transmission speed within a certain range determined to minimize EMI.
A liquid crystal panel driving apparatus according to still another preferred embodiment of the present invention includes a data input arranged to input video data, source driving circuits arranged to drive data lines in a liquid crystal panel, and a data interface unit arranged to transmit the video data to the source driving circuits such that a data transmission speed is varied to minimize EMI.
A liquid crystal panel driving apparatus according to still another preferred embodiment of the present invention includes a data input arranged to input video data synchronized with a desired frequency of data clock, source driving circuits arranged to drive data lines in a liquid crystal panel, a clock modulator arranged to modulate the data clock to provide a modulated clock having a frequency which is varied so as to minimize EMI, and a data timing controller responsive to the data clock and the modulated clock to transfer the video data to the source driving circuits such that a data transmission speed is varied within a certain range determined for minimizing EMI.
A monitor apparatus according to still another preferred embodiment of the present invention includes a data input arranged to input a video data, a data driver arranged to drive data lines with the video data, and a data scaling unit arranged to scale the video data from the data input and to supply scaled video data to the data driver such that a data transmission speed is varied within a certain range determined for minimizing EMI.
A monitor apparatus according to still another preferred embodiment of the present invention includes a data input arranged to input video data synchronized with a certain frequency of a data clock, a data driver arranged to drive data lines with the video data, a clock modulator arranged to modulate the data clock to provide a modulated clock having a frequency which is varied within a certain range of frequency band located around a desired target frequency, and a data scaling unit arranged to respond to the data clock and to scale the video data from the data input and to respond to the modulated clock to supply scaled video data to the data driver in such a manner that a data transmission speed is varied within a certain range to minimize EMI.
A monitor apparatus according to still another preferred embodiment of the present invention includes a signal converter arranged to convert an analog video signal into a digital video data, a data driver arranged to drive data lines with the video data, a clock generator arranged to generate a sampling clock, a clock modulator arranged to modulate the sampling clock into a modulated clock having a frequency which is varied within a certain range of frequency band and applying the modulated clock to the signal converter, to thereby vary a transmission speed of the digital data within a certain speed range selected to minimize EMI, and a data scaling unit arranged to scale the video data from the signal converter and to supply the scaled video data to the data driver.